Skip to content

1G MAC Interface

Andrew W. Moore edited this page Mar 13, 2012 · 3 revisions

Name

nf10_1g_interface

Version

v1.00a

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_1g_interface_v1_00_a/

Interface Types

SGMII, AXI4-Stream

Bus

M_AXIS_0, M_AXIS_1: Master AXI4-Stream (RX) bus, 8bit

S_AXIS_0, S_AXIS_1: Slave AXI4-Stream (TX) bus, 8bit

M_AXIS_ERR_0, M_AXIS_ERR_1: Master AXI4-Stream (ERR) bus, 0bit, handshake only

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream (RX) bus. Must be 8

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream (TX) bus. Must be 8

Register map

No registers are implemented for v1.00a.

Description

This pcore is a combination of Xilinx Vitex-5 Embedded Tri-mode Ethernet MAC (TEMAC) and an AXI4-Stream adapter. Incoming SGMII signals from AEL2005 are received by the TEMAC and finally transformed into AXI4-Stream. The TX side follows the exact same path but in the opposite direction. Although we use "Tri-mode" MAC, due to the limitation of AEL2005, only Gigabit Ethernet mode is supported.

The Virtex-5 Embedded Tri-mode Ethernet MAC is a dual-MAC hard IP. Hence, each pore has two independent groups of buses, corresponding to each MAC.

There is one additional AXI4-Stream bus for transmitting bad_frame signal provided by Xilinx TEMAC. For more information about NetFPGA Standard IP Interfaces, please see here.

External references

  1. AXI Spec: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html

  2. Xilinx 10G MAC: http://www.xilinx.com/products/ipcenter/V5_Embedded_TEMAC_Wrapper.htm

Clone this wiki locally
You can’t perform that action at this time.