Release Notes

Neelakandan Manihatty Bojan edited this page Apr 7, 2015 · 1 revision
Clone this wiki locally

NetFPGA 10G v5.0.7

NetFPGA 10G v5.0.6

NetFPGA 10G v5.0.5

  • Added the Reference Router GUI interface: The Java GUI allows the user to change entries in the Routing Table and ARP cache as well as the router's MAC and IP addresses. It also provides updates on counter values and graphs of throughput and much more.

    wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Reference-Router

  • Updated statistics for packets droped counter at the interface.

NetFPGA 10G v5.0.4

  • Project related information stored in the bitfile

    We have updated the nf10_identifier module to store information related to date and time the synthesis started, board id, release tag, project identification, project features and misc details. So that once the bitfile is loaded in the FPGA, the driver can parse these registers and give some useful information to the users.

    wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/Project-related-information-in-bitfiles

NetFPGA 10G v5.0.3

NetFPGA 10G v5.0.2

NetFPGA 10G v5.0.1

  • HW tests for reference router:

    • Following are the tests for reference_router.

    both_badipchksum_packet
    both_lpm_generic
    both_nonip_packet
    both_router_table both_invalidttl_packet
    both_lpm_misses
    both_nonipv4_packet
    both_wrong_destMAC both_arp_misses
    both_ipdestfilter_hit
    both_lpm_nexthop
    both_packet_forwarding

    wiki for router tests: https://github.com/NetFPGA/NetFPGA-public/wiki/Tests-for-reference-router

    wiki for simulation infrastructure: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Simulations

    wiki for HW test infrastructure: https://github.com/NetFPGA/NetFPGA-public/wiki/HW-Tests

  • Updated the Makefiles of reference projects:

    • to remove residual files when doing a "make clean".
    • renaming the bitfiles in accordance with the name of the project.

    wiki for register monitoring system: https://github.com/NetFPGA/NetFPGA-public/wiki/Register-Monitoring-System

  • Updated xparam2regdefines.py to remove the "_OFFSET" suffix in the register names. Also updated the software monitoring system files to keep them in sync with the changes.

  • Driver fixes and updates:

    • removed libnl source code (from nic_oped contrib project). As modern OS have their own libnl packages (for Fedora it's called libnl3). It can be installed by yum install libnl3.
    • removed the copy of driver files in reference_nic_1g.
    • updated nic_oped driver to support kernel 3.12.5.
    • removed unused attributes of nf10driver.c in reference_nic driver.

NetFPGA 10G v5.0.0

NetFPGA 10G v4.9

This is a major release in the series of releases for the NetFPGA-10G beta community. It has the following new features:

  • Reference Router:

  • PCIE programming:

  • HW tests.

    • Python based HW Tests for for reference_nic, reference_switch, reference_switch_lite. Contains the following: bashrc (global), Python library (global top level library), Python library (project specific library containing register defines), python parser (to convert xparameters.h to reg_defines.py), Test folder (project specific contains conn, global and hw tests files), Shared library(global library)

      Documentation : https://github.com/NetFPGA/NetFPGA-public/wiki/HW-Tests

  • Partial synthesis

  • New pcores :

    The following pcores have been added

    • nf10_identifier_v1_00_a -- used to identify (gives the project name, time and date of creation, git release tag) the bitfile loaded in the FPGA
    • nf10_input_arbiter_v1_10_a -- input arbiter with registers
    • nf10_10g_interface_v1_20_a -- nf10_10g interface with registers to check only good packets.
    • nf10_bram_output_queues_v1_01_a -- BRAM ouput queues with fix from Shahbaz
    • nf10_bram_output_queues_v1_10_a -- BRAM output queues with registers
    • nf10_router_output_port_lookup_v1_10_a -- router output port look up with registers
  • Driver:

    • Driver updated to fix multiple threads reading/writing axi registers

NetFPGA 10G v4.8

This is the sixth release in the series of releases for the NetFPGA-10G beta community. It has the following new features:

  • Updated DMA core for reference projects
    • The reference projects (reference_nic,reference_nic_1G,reference_switch,reference_switch_lite and reference_flash) have been updated with a new DMA core. The reference_nic project in the previous release_4.7.1 (utilizing the OPED core) has been moved to the contrib_projects as nic_oped.
  • SW update (nf10_switch) for Reference Switch and Reference Switch Lite
    • New software tools to read the LUT hit and miss registers can be found inside the the specific project's /sw/host/nf10_switch folder.
  • Production test
    • Updated the config file and production scripts to support different com ports for UART testing.
  • New naming convention to identify projects using OPED core in the contrib_projects
    • "{project_name}_oped" postfix has been appended to projects utilizing the OPED core.
  • Reference Router
    • Reference_router project is under the testing phase and requires some SW update. We are working on it and planning for its release shortly.

NetFPGA 10G v4.7

This is the fifth release in the series of releases for the NetFPGA-10G beta community. It has the following new features:

  • Reference Switch
    • Learning switch with TCAM (doesn't support full learning at 40G line rate for small packets, i.e. 64KB)
  • Reference Switch Lite
    • Learning switch with Registers (40G line rate)
  • Ported IPv4 Router
    • 10G IPv4 router using the NetFPGA 1G pipeline
  • SCONE
    • Port of SCONE for the 10G router designs
  • Router Kit
    • Port of Router Kit for 10G router designs
  • Router CLI
    • Port of the CLI for 10G router Designs
  • Generic Regs and Tables in HW
    • Register and table access using generic implementation
  • NetFPGA-10G patch for XAPP852
    • RLDRAM II regression testing
  • DRAM memory-mapped interface
    • AXI4 to RLDRAM II for data/instruction memory
  • ARP Reply
    • AXI implementation of ARP reply with example project
  • Encap/Decap
    • AXI implementation of Encap/Decap with example project and GUI

Few of the limitations that still persist are:

  • FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

NetFPGA 10G v4.6

This is the forth release in the series of releases for the NetFPGA-10G beta community. It includes following new features:

  • Reference 10G Learning CAM Switch
  • Simple 10G Switch

Few of the limitations that still persist are:

  • FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

NetFPGA 10G v4.5

This is yet another release in the series of releases for the NetFPGA-10G beta community. It provides following new features:

  • OpenFlow Switch v1.0
  • Register System (based on EDK workflow)
  • SRAM FIFO
  • Official support for Xilinx 13.4 suite

Few of the limitations that still persist are:

  • FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

NetFPGA 10G v4.4 (Inishmore)

This is the second one in the series of releases for the NetFPGA-10G beta community. It contains following new features:

  • Faster and smaller implementation of PCIe DMA Egine and Device Driver.
  • Mechanics for porting NetFPGA-1G reference pipeline to the 10G platform.
  • Improved R/W timing for Flash ICs. Now takes around 5 mins to program each flash.

Few of the limitations that still persist are:

  • The nf10_configure utility will enter an indefinite held state if the NF10 driver is not installed.
  • FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

Bug fixes

  • Input Arbiter - a dead lock condition occurs for AXI Stream between two modules [resolved]

NetFPGA 10G v4.3

This is the first release published after the NetFPGA-10G has transition into beta. Contains all the features of its predecessors and is now available to a wider community.

NetFPGA 10G v4.2 (Isle of Man)

Isle of Man is another early release to the NetFPGA-10G alpha community. It contains a new feature of flash configuration. The projects are fully functional and tested, but there are few additional limitations listed below:

  • Programming each Flash IC takes around 30 mins.
  • The nf10_configure utility will enter an indefinite held state if the NF10 driver is not installed.
  • FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

The golden images (bitstreams) will not be present in the later releases. They will be provided as a separate link to reduce the overall size of the release.

NetFPGA 10G v4.1 (Skellig)

Skellig is an early release to the NetFPGA-10G alpha community. The designs in this projects are fully functional and tested, however we would like to point out the following issues:

  • The reference NIC in 1G and 10G designs operate reliably however with a low throughput. Please check the following page for more details: NIC's Benchmark
  • When running the system level simulation (make sim) for the reference_nic, we currently encounter a potential bug with isim which corrupts the outputs in the log file: nf10_oped_0_log.axi. If needed, use Modelsim until this bug is resolved.
  • Flash configuration is not contained in this release.