Releases: llvm/circt
Releases · llvm/circt
Firtool Release 1.46.0
What's Changed
- [Dedup] Parallelize hash calculation, NFCI by @uenoku in #5518
- [FIRRTL] Delete force/release statements with constant-false predicates. by @dtzSiFive in #5555
- [FIRRTL][LowerXMR][NFCI] Minor touchups. by @dtzSiFive in #5549
- [Arc] Fix header generation when depth is -1 by @zyedidia in #5501
- [FIRParser] Allocate subParser on heap by @uenoku in #5560
- [FIRRTL] Allow strictconnect to have different but structurally equivalent types by @uenoku in #5515
- [Support/ESI] Add generic port conversion utility by @mortbopet in #5533
- [FIRRTL][LowerXMR] Support ref.sub. by @dtzSiFive in #5551
- [FIRRTL][FIRParser] Parse rwprobe to element of aggregate. by @dtzSiFive in #5550
- [FIRRTL][LowerXMR] Include forceable + force/release ops in zero-width handling. by @dtzSiFive in #5553
- Emit companion Assumes for UNR Only SVAs as Immediate (instead of concurrent) by @girishpai in #5561
- [FIRRTLToHW] Lower memories to seq.firmem by @fabianschuiki in #5025
- [Pipeline] Refactor pipeline ops to include naming info by @mortbopet in #5548
- [HW/SV] Add
hw.inout
elimination pass by @mortbopet in #5390 - [FIRRTL][LOA][NFC] Tweak structure dump/print. by @dtzSiFive in #5570
Full Changelog: firtool-1.45.0...firtool-1.46.0
Firtool Release 1.45.0
What's Changed
- [LowerIntrinsics] Touchup to avoid unused instance path cache. by @dtzSiFive in #5411
- [Comb] Truth table operation by @teqdruid in #5404
- [OM] Expose ReferenceAttr to Python by @nandor in #5413
- [FIRRTL][InferWidths] Tweak debug printing to show names and more bits. by @dtzSiFive in #5415
- [FIRRTL] Clean up instances in ExtractClasses. by @mikeurbach in #5395
- [CI] Push circt python wheel to pypi nightly by @rsetaluri in #5412
- [Pipeline] Add verifiers and fix register materialization pass by @mortbopet in #5386
- [Pipeline] Add "ext" inputs to pipelines by @mortbopet in #5347
- [DCToHW] Add DCToHW conversion pass by @mortbopet in #5298
- [FIRRTL] ExtractClasses: Fix use-after-free. by @dtzSiFive in #5429
- [Reduce] Add missing build deps on HW/FIRRTL dialects. by @dtzSiFive in #5430
- [CAPI][NFC] Address function prototype warnings by @trilorez in #5432
- [Python] Fix import path by @teqdruid in #5434
- [PyCDE] Fix parameterized extern mods by @teqdruid in #5435
- [Comb] Lower comb pass boilerplate by @teqdruid in #5433
- [LowerComb] Truth table to mux tree lowering by @teqdruid in #5405
- [FIRRTL] Support EnumTypes in error messages by @youngar in #5439
- PTECH-747: llvm bump on circt. Found 2 errors. by @mbalboni07 in #5414
- [Seq] Add
seq.fifo
ODS and rationale by @mortbopet in #4189 - [CMake] Make cmake config more reliable? by @maerhart in #5145
- [FIRRTL] Add mux cell intrinsics by @uenoku in #5428
- [FIRRTL] Add BaseTypeAliasType by @uenoku in #5416
- [ExportVerilog] Remove array literal by @uenoku in #5443
- [FIRRTL][InferResets] Fix reset inference through const cast. by @dtzSiFive in #5370
- [HW] Add struct_create(struct_explode) folder by @maerhart in #5450
- [CI][Win] Reduce peak disk usage after LLVM rebuild. by @dtzSiFive in #5446
- [Seq] Add FirMem op by @fabianschuiki in #5009
- Bump LLVM along Main by @mwachs5 in #5451
- [FIRRTL] Implement alias-aware type casts by @uenoku in #5417
- [FIRRTL] Options for using both @info and .fir, attach .fir as notes. by @dtzSiFive in #4671
- [Seq] Fix FirMemReadWriteOp::canonicalize by @trilorez in #5460
- [SVExtractTestCode] Clone constants even when used by designs as well by @uenoku in #5466
- [SVExtractTestCode] Use name/namehint as a port name by @uenoku in #5464
- [FIRRTL] Reset values added in InferResets are now const. by @trilorez in #5468
- [SeqToSV] Add
clock_gate
lowering by @mortbopet in #5457 - [Pipeline] add 'go' signal to pipeline by @mortbopet in #5455
- [Pipeline] Add preliminary stall lowering by @mortbopet in #5467
- [FIRRTL] Add type alias parser by @uenoku in #5449
- [FIRRTL] Drop unused repl-seq-mem-circuit option. by @dtzSiFive in #5474
- [Seq] Lower FirMemOp to HWModuleGeneratedOp by @fabianschuiki in #5024
- [Calyx] Add sequential memories by @andrewb1999 in #5471
- [FIRRTL][CHIRRTL] Add dialect C API by @SpriteOvO in #5472
- [FIRRTL] Support instances of property modules in ExtractClasses. by @mikeurbach in #5396
- [FIRRTL][CHIRRTL] C API rename and change some types by @SpriteOvO in #5486
- [NFC][Pipeline] Restructure pipeline dialect tablegen files by @mortbopet in #5475
- [Arc] Eliminate
AllocateState
moveBefore
/isBeforeInBlock
combination by @TaoBi22 in #5481 - [FIRRTL][NFC] Add test rejecting connect of properties. by @dtzSiFive in #5491
- Add support for Windows and revamp FIRRTL release artifacts by @jackkoenig in #5470
- [FIRRTL][NFC] Fix typo in Vector type parameter. by @dtzSiFive in #5495
- [FIRRTL][Properties] Add List, Map<K, V> types. by @dtzSiFive in #5492
- [circt-lec] Fixed equivalence check for multiple outputs by @fzi-hielscher in #5358
- [FIRRTLToHW] Add missing twoState attributes by @fzi-hielscher in #5257
- [FIRRTL][CreateSifiveMetadata] Use symbols for memory metadata by @prithayan in #5482
- [SV] Cleanup HWExportModuleHierarchyPass by @seldridge in #5485
- [FIRRTL] Export literal identifiers correctly by @seldridge in #5502
- [InferWidth] Parallelize post processing, NFCI by @uenoku in #5496
- [Comb][ExportVerilog] Support SV attributes for MuxOp by @uenoku in #5487
- [FIRRTL][FIRParser] Rework assert+FALLTHROUGH, NFCI. by @dtzSiFive in #5505
- [FIRRTL] Verify OpenAggs, fix agg-of-properties. by @dtzSiFive in #5508
- [FIRRTL][IMDCE] Remove some cached state by @youngar in #5480
- [LowerFIRRTLToHW] Create less wires with instance ports by @youngar in #5510
- [FIRRTL][IMDCE] Add test for dead output ports, NFC by @youngar in #5512
- [LowerFIRRTLToHW] Use backedges over temporary wires, NFC by @youngar in #5513
- [FIRRTL] Add FIRRTLTypeSwitch by @uenoku in #5456
- [IMDCE] Delete unreachable modules by @uenoku in #5517
- [Arc] Fix dominance issue in GroupResetsAndEnables by @zyedidia in #5511
- [FIRRTL] Canonicalize reductions looking through casts of various forms by @darthscsi in #5499
- [InstanceGraph] Speed up instance graph constructions, NFCI by @uenoku in #5520
- [FIRRTL][FIRPaser] Better diagnostic for unsupported rwprobe's. by @dtzSiFive in #5522
- [InferWidths] Remove expensive walks, NFC by @uenoku in #5523
- [ExportChiselInterface] Support probe types by @trilorez in #5497
- [FIRRTL] Change emitter to v3.0.0 by @seldridge in #5509
- [Calyx] Add Static Groups and Control by @andrewb1999 in #5354
- [PyCDE] Upgrade FSMs to new module style by @teqdruid in #5516
- [LLVM] Weekly bump by @maerhart in #5503
- [FIRRTL] Add containTypeAlias to type storage and define
getAnonymousType
by @uenoku in #5493 - [Pipeline] Add per-register clock gating by @mortbopet in #5489
- [LowerToHW] Implement MuxCell intrinsics lowering by @uenoku in #5458
- [InferReset] Parallelize the annotations accumulation, NFC by @uenoku in #5534
- [FIRRTL] Canonicalize away CVT and adjust all patterns which matched cvt by @darthscsi in #5527
- [FIRRTL] Remove UninferredWidthCastOp for now. by @dtzSiFive in #5528
- [Support] Add a 'by-name' lookup for HWModuleLike ops by @mortbopet in #5473
- [Comb][Canonicalize] keep attributes during op width narrowing by @7FM in #5532
- [Pipeline] Fix
ScheduledPipelineOp
builder by @mortbopet in #5540 - [Seq] Canonicalize transitive clock gates by @mortbopet in #5504
- [SCF-to-Calyx] Fix Ordering Bug by @calebmkim in #5526
- Bump LLVM to 015dabd7672f936cdb5bdcad20fe80b17f05c9ca by @mikeurbach in #5546
- [HW] Fix instance ops in
hw-flatten-io
pass by @mortbopet in #5537 - [FIRRTLFolds] Fix
andr(pad(x:sint, n)) -> andr(x)
canonicalization by @uenoku in #5547 - [FIRRTL] incorrect canonicalization pattern by @darthscsi in #5556
New Contributors
- @mbalboni07 made their first contribution in #5414
- @fzi-hielscher made their first contribution in #5358
- @calebmkim made their first contribution in #5526
Full Changelog: https://github.com/llvm/circt...
Firtool Release 1.44.0
What's Changed
- [Reducer] Speed up OperationPruner by @maerhart in #5311
- [Pipeline] Fix use-after-free in StageSeparatorToStagePass. by @dtzSiFive in #5313
- [FIRRTL] Add Verif/LTL intrinsics by @fabianschuiki in #5310
- [OM] Bypass constant ops referencing symbols in
ExportVerilog
by @nandor in #5314 - [MapArith] Introduce
--map-arith-to-comb
pass by @mortbopet in #5297 - [IMCP] Speed up the bulk connection propagation, NFCI by @uenoku in #5290
- [NFC] LLVM bump by @darthscsi in #5317
- [FIRRTL] Add util support for refsub/open aggs by @dtzSiFive in #5315
- Enum const support by @trilorez in #5321
- Preserve const for getWidthlessType by @trilorez in #5328
- [Pipeline] Add integration test by @mortbopet in #5281
- [Capnp] Move the minimum CMake version logic to only run if capnp is found by @teqdruid in #5335
- [ETC] Extract registers and instances if not in design by @uenoku in #5331
- [OM] Use standard API for getting the base pointer from a vector. by @mikeurbach in #5338
- [Calyx to FSM]Fix the bug when calyx multi-component design lower to fsm. by @linuxlonelyeagle in #5341
- [Python] Add CMake for MacOS C++17 compatibility in wheel build. by @mikeurbach in #5343
- Update FIRRTLAnnotations.md to remove reference to tb_seq_mems.json [NFC] by @mwachs5 in #5342
- [FIRRTL] Make StringType buildable by @youngar in #5344
- [FIRRTL] Add StringConstantOp by @youngar in #5345
- [Comb] Canonicalize a + c1 + c2 into a + (c1 + c2) by @nandor in #5348
- [Comb][FIRRTL][Seq] Fix fusing locations to append not add as metadata. by @dtzSiFive in #5349
- [FIRRTL] Donot rename InstanceOp by @prithayan in #5352
- [SV][ETC] Fix perf bug removing from a SetVector of slice results. by @dtzSiFive in #5353
- [DependenceAnalysis] Check memref dependencies on each loop nest by @matth2k in #5287
- [Arc] Preserve extern modules as internal inputs/outputs by @fabianschuiki in #5069
- [ETC] Don't erase operations used by dead module instances by @uenoku in #5357
- [Pipeline] Refactor pipeline dialect to be block-based by @mortbopet in #5332
- [FIRRTL] Add property assign op instead of using connect by @youngar in #5361
- [FIRParser] Add support for parsing String types by @youngar in #5362
- [FIRParser] Parse PropAssignOps by @youngar in #5365
- [FIRRTL] Explicitly reject rwprobe of types containing const. by @dtzSiFive in #5367
- [FIRRTL][IMDCE] Remove dead operation from live set. by @dtzSiFive in #5369
- [FIRParser] Parse string constants by @youngar in #5368
- [FIRRTL][ExpandWhens] Support properties by @youngar in #5373
- [FIRRTL] Improve PropAssignOp verifiers by @youngar in #5375
- [FIRRTL] Add RefCastOp for reset/width/const differences in refs. by @dtzSiFive in #5372
- [FIRRTL][InferWidths] Skip over property types by @youngar in #5381
- [Pipeline] Add optional
stall
signal to pipelines by @mortbopet in #5278 - [Pipeline] Add
pipeline.latency
operation by @mortbopet in #5340 - [Pipeline] Remove LI notion from pipelines by @mortbopet in #5359
- [FIRRTL] Add utility for getting the assignment to a property value. by @mikeurbach in #5374
- [ExportFIRRTL] Implement C API by @SpriteOvO in #5300
- [LowerToHW] Lower clock gate intrinsic to Seq dialect by @fabianschuiki in #5363
- [FIRRTL][LowerXMR] Resolve through refcast operations. by @dtzSiFive in #5376
- [FIRRTL][IMCP] Skip over non-base types by @youngar in #5382
- [FIRRTL][InferWidths] Handle foreign and prop types uniformly by @youngar in #5392
- [FIRRTL][CheckCombLoops] Support property types by @youngar in #5383
- [FIRRTL] Add BigInt property type by @youngar in #5384
- [FIRRTL][LowerTypes] Support RefCast. by @dtzSiFive in #5377
- [FIRRTL][InferWidths] Support RefCastOp. by @dtzSiFive in #5378
- [FIRRTL][InferResets] Support RefCastOp. by @dtzSiFive in #5387
- [FIRParser] Add support for BigInt types by @youngar in #5385
- [FIRRTL] Add v2.4.0 Radix-specified Integer Literals by @seldridge in #5380
- [FIRRTL] Support const "source" in forces, insert refcast as needed. by @dtzSiFive in #5388
- [FIRRTL][FIRParser] Support define of non-identical refs via ref.cast. by @dtzSiFive in #5389
- [Seq] Add clock gate conversion to extern module by @fabianschuiki in #5364
- [FIRRTL] Add BigIntConstantOp by @youngar in #5397
- [FIRParser] Support BigInt constants by @youngar in #5398
- [FIRRTL] Remove
getBaseTypeOrNull
by @youngar in #5393 - [OM] Simplify the Python instantiate API to just return Objects. by @mikeurbach in #5400
- [FIRRTL][InferWidths] Fix back-prop, fix ref equality, fix upper bound. by @dtzSiFive in #5403
- [FIRRTL] Use preferred cast style, NFC by @uenoku in #5401
- [FIRRTL] Initial pass to extract OM classes from FIRRTL modules. by @mikeurbach in #5394
- [FIRRTL] Introduce a helper ODS class for type declaration, NFC by @uenoku in #5399
- [HW] Fix type casts for nested type alias by @uenoku in #5339
- [FIRRTL] Replace deprecated casts in tablegen, NFC by @uenoku in #5406
- [FIRRTL][InferWidths] Restore back-prop constraint for strictconnect. by @dtzSiFive in #5409
- [FIRRTL] Delete CheckCombCycles, remove -use-old-check-comb-cycles. by @dtzSiFive in #5410
- [OM] Get the field names from an Object by @prithayan in #5402
New Contributors
- @linuxlonelyeagle made their first contribution in #5341
Full Changelog: firtool-1.43.0...firtool-1.44.0
Firtool Release 1.37.1
What's Changed
- Backport IMDCE improvements into firtool 1.37 by @uenoku in #5318
- [ModuleInliner][BugFix] Correctly update NLA after recursive inline (… by @uenoku in #5330
Full Changelog: firtool-1.37.0...firtool-1.37.1
Firtool Release 1.34.4
What's Changed
Full Changelog: firtool-1.34.3...firtool-1.34.4
Firtool Release 1.43.0
What's Changed
- [DC] Add canonicalization patterns by @mortbopet in #5158
- [circt-lec] Clean up z3 includes by @rwy7 in #5186
- [FIRRTL] Export named references as macros to Verilog files by @trilorez in #5180
- [Arc] Change MemoryWritePortOp to also take an arc by @maerhart in #5166
- [Arc] Add ArcCanonicalizer pass by @maerhart in #5196
- [arcilator] Convenience flag for printing debug info by @maerhart in #5199
- [Arc] Simulation specific optimization for comb.icmp by @maerhart in #5198
- [Arc] Merge RemoveArcArgsPattern into ArcCanonicalizer by @maerhart in #5200
- [Arc] SinkInputs: update to CallOpMutableInterface and merge into ArcCanonicalizer by @maerhart in #5201
- [OM] Add initial implementation of Evaluator. by @mikeurbach in #5193
- [FIRRTL] Add a type interface for querying phase compatibility by @rwy7 in #5206
- [FIREmitter] Support Open aggregates, RefSubOp by @dtzSiFive in #5179
- [FIRRTL] Handle flips in const connections by @trilorez in #5210
- [DC] Add fork/sink materialization passes by @mortbopet in #5159
- [LowerSeqToSV] Fix a dominance bug when restoring subaccess by @uenoku in #5215
- [DC] Address canonicalizer review comments by @mortbopet in #5212
- Add StringType to FIRRTL dialect by @rwy7 in #5208
- [SV] Add lowering option to emit separate always blocks by @nandor in #5211
- [FIRRTL] Const handling in cast ops by @trilorez in #5151
- [WireDFT] Add support for wiring optional clock div bypass signal. by @dtzSiFive in #5219
- [NFC][ESI][C++ API] Cleaning up more references to 'cosim' by @teqdruid in #5227
- Bump LLVM by @girishpai in #5228
- [DC] Add merge operation by @mortbopet in #5213
- [HandshakeToDC] Add conversion by @mortbopet in #5214
- [Seq][HW] Add a macro to enable register initializers by @nandor in #5222
- [ExportVerilog] Fix formatting involving macro definition. by @dtzSiFive in #5232
- [FIRRTL][LowerXMR] Use ABI for refs when no internal path info. by @dtzSiFive in #5229
- [FIRRTL] Reject ref statements for some ports but not all. by @dtzSiFive in #5233
- [OM] Add a symbol reference attribute by @prithayan in #5230
- [CI] Add runs with Valgrind to CI by @nandor in #5085
- [HW][SV] Allow control of initial blocks setting memories by @nandor in #5237
- [OM] Add helper builders for OM ops by @prithayan in #5244
- [firtool] Separated firtool pipeline setup into a library by @nandor in #5241
- [HWCleanUp] Don't fuse always_comb by @uenoku in #5175
- [SystemC] integration tests: avoid compile_commands.json in clang-tidy. by @dtzSiFive in #5239
- [CI] Add macos wheels by @rsetaluri in #5249
- [LowerSeqToSV] Remove Vivado workaround by @uenoku in #5245
- [OM] Add initial CAPI for OM dialect Evaluator. by @mikeurbach in #5248
- [circt-lec] Move
circt-lec
files to CIRCT library by @TaoBi22 in #4544 - [FIRRTL] Make emit-metadata a mlir::ModuleOp pass by @prithayan in #5247
- [OM] Add initial Python API for OM dialect evaluator. by @mikeurbach in #5250
- [FIRParser] Support keywords and literal identifiers as static ref exprs. by @dtzSiFive in #5252
- Bump LLVM by @uenoku in #5251
- [CMake] Require cmake >= 3.23 but only on capnp builds by @teqdruid in #5243
- [IMDCE] Remove dead hierpath and annotations in IMDCE by @uenoku in #5226
- [PrefixModules] Rename references from the module body by @nandor in #5259
- Make Z3 a transitive dependency of CIRCTLogicalEquivalence by @rwy7 in #5261
- [FIRRTL] DropConst pass by @trilorez in #5152
- [cmake] Gate FILE_SET commands on CAPNP by @teqdruid in #5265
- [FIRParser] Add support for enumeration types and match statements by @youngar in #5116
- [Arc] Improve icmp canonicalization pattern by @maerhart in #5266
- Remove explicit phase annotations by @rwy7 in #5262
- [Python] Enable release tag by @rsetaluri in #5254
- Move from defunct codeowners to GitHub CODEOWNERS. by @dtzSiFive in #5269
- [CI] Migrate from set-output to using environment files. by @dtzSiFive in #5267
- [CI] Update github actions for checkout, cache: v2 -> v3 by @dtzSiFive in #5268
- [CI] Update upload-artifact action v2 -> v3, already using in other flows. by @dtzSiFive in #5271
- Force all XMRRefs to go through hierpath by @darthscsi in #5220
- Add LTL and Verif dialects by @fabianschuiki in #5255
- [ExportVerilog] Add LTL and Verif dialect support by @fabianschuiki in #5256
- Move cocotb driver to separate tool by @mortbopet in #5279
- [FIRRTL] Tweak naming by @darthscsi in #5288
- [OM] Use custom CAPI wrappers for Object. by @mikeurbach in #5275
- [OM] Add Python support for Objects in Fields. by @mikeurbach in #5276
- [FIRRTL][ExpandWhens] Fix performance with large blocks by @youngar in #5293
- [IMCP] Mark overdefined for the operations with large number of operands by @uenoku in #5291
- [OM] Add a string type by @uenoku in #5277
- [OM] Add a list type and attribute by @uenoku in #5280
- [FIRRTL] Donot create empty InnerSym name by @prithayan in #5301
- [FIRRTL][ModuleInliner] Donot create empty inner sym by @prithayan in #5302
- [Pipeline] Add
pipeline.stage
op and rename others accordingly by @mortbopet in #5246 - [PipelineToHW] Rework hardware lowering by @mortbopet in #5234
- [LowerSeqToSV] Make
createTree
iterative, NFCI by @uenoku in #5303 - [FIRRTL] Const parsing, emitting, and prim ops by @trilorez in #5153
- [Pipeline] Fix constant copying in StageSeparatorToStage by @mortbopet in #5308
- [Arc] Pull value definitions into reset/enable
IfOp
s where possible by @TaoBi22 in #5188 - [OM] Add ClassOp builders by @prithayan in #5283
- [Verif] Add assert/assume/cover labels by @fabianschuiki in #5306
- [OM] Create OM Nodes for metadata by @prithayan in #5224
- [FIRRTL][InferWidths] Make solveExpr Iterative by @prithayan in #5305
- [comb] Minor correction to
comb.icmp
td docs by @TaoBi22 in #5304
New Contributors
- @girishpai made their first contribution in #5228
Full Changelog: firtool-1.42.0...firtool-1.43.0
Firtool Release 1.34.3
What's Changed
- (1.34.3 backport) [WireDFT] Add support for wiring optional clock div bypass signal. (#5219) by @dtzSiFive in #5225
Full Changelog: firtool-1.34.2...firtool-1.34.3
Firtool Release 1.42.0
Please note, the previous release of firtool, firtool-1.41.0
has a compilation error. Please use this release instead.
What's Changed
- [CI] Add python3.8 manylinux wheel by @rsetaluri in #5174
- [FIREmitter] Use PrettyPrinter for breaking/indenting. by @dtzSiFive in #5176
- [HWArithToHW] Restore access to HWArith-specific patterns. by @jopperm in #5185
- [firtool] Erase extra verbatim files before printing final MLIR. by @mikeurbach in #5181
- [FIRRTL] Fix connect verifier for enums by @youngar in #5183
- [Arc] MemoryReadPortOp: remove enable and clock operand, make it pure by @maerhart in #5194
- [Arc] Fix arc.output verifier by @maerhart in #5197
- [Arc] Include the addressing type in the memory type by @maerhart in #5195
Full Changelog: firtool-1.41.0...firtool-1.42.0
Firtool Release 1.41.0
What's Changed
- [LowerTypes] Preserve rwprobes, forceable. by @dtzSiFive in #5051
- [FIRRTL] Support AttributeAnnotation by @uenoku in #5076
- [ESI] Refactor ESI cosim API type emission by @mortbopet in #5096
- [ESI] Add clean metadata pass by @mortbopet in #5097
- [ESI] Add --server-only mode to esi-cosim-runner.py by @mortbopet in #5098
- [ESI] Add C++ cosimulation API by @mortbopet in #5099
- [ESI] Add C++ cosimulation capnproto backend by @mortbopet in #5100
- [FIRRTL][LowerTypes] Use agg create ops for unlowered users. by @dtzSiFive in #5101
- [FIRRTL] Register const updates by @trilorez in #5074
- Bump LLVM by @trilorez in #5095
- [Arc] LowerState: fix memory read materialization by @zyedidia in #5094
- [reduce] Handful of reducer fixes and improvements by @fabianschuiki in #4100
- [HWMemSimImpl] Remove "mem" from "ignore-read-enable-mem" flag by @fabianschuiki in #3538
- [ExportVerilog] Remove unused function by @youngar in #5106
- [HW] Add verifiers for EnumConstantOp and EnumCmpOp by @youngar in #5105
- [FIRRTL] Introduce element-wise operations by @uenoku in #4636
- [circt-lec] Introduce the
circt-lec
tool by @frog-in-the-well in #3991 - [docs] Fix broken docs links in PyCDE and diagrams on Getting Started page by @VMois in #5013
- [FIRRTL] Fix enumcreate printed form by @youngar in #5117
- [firtool] Run LowerMatches before InferWidths by @youngar in #5118
- [ExportVerilog] Transform anonymous enumerations in to typedefs by @youngar in #5107
- [HandshakeToHW] Add
handshake.instance
lowering by @mortbopet in #5113 - [ESI] ESI CPP Cosim API -> ESI CPP API by @mortbopet in #5115
- [ExportVerilog] Add option to disallow packed struct assignments by @mortbopet in #5114
- [HW] Remove
getGroundFields
fromFieldIDTypeInterface
by @youngar in #5126 - [FIRRTL] Support FEnumTypes in FIRRTLBaseType dispatch functions by @youngar in #5123
- [FIRRTL] Hoist common type-property methods up to FIRRTLType. by @dtzSiFive in #5125
- [FIRRTL][LowerMatches] Fix matches with 0 and 1 variants by @youngar in #5124
- Update RationaleFIRRTL.md by @mmaloney-sf in #4911
- [HW] Support enum types in
hw::getBitWidth()
by @youngar in #5129 - [Arc] Add clock_domain canonicalizer by @maerhart in #5018
- [Docs] Update dialect diagram by @maerhart in #4122
- [Arc] Fix ClockDomainOp canonicalizer by @maerhart in #5133
- [circt-reduce] Infrastructure improvements, bug fixes, and additional tests by @maerhart in #5131
- [circt-reduce] Fix tests for portability again, prefer /usr/bin/env. by @dtzSiFive in #5135
- [FIRRTL][InferResets] Fix inference through ref.sub. by @dtzSiFive in #5136
- [Docs] Add Arc to dialects diagram by @maerhart in #5134
- Make FModuleLike inherit from HWModuleLike by @rwy7 in #4659
- bump llvm by @debs-sifive in #5120
- [HandshakeToFIRRTL] <- deprecate by @mortbopet in #5130
- [firtool][circt-as] Handle new error result for writeBytecodeToFile. by @dtzSiFive in #5140
- [Arc] Add LatencyRetiming pass by @maerhart in #5141
- [FIRRTL] Add Open variants of vector/bundle, subindex/subfield. by @dtzSiFive in #5127
- [FIRRTL] Add verifiers for rwprobe + const on RefType, Forceable. by @dtzSiFive in #4982
- [Arc] Add StorageGetOp canonicalizer by @maerhart in #5147
- [Arc] Add IsolateClocks pass by @maerhart in #5146
- [Arc] Generalize InlineArcs pass by @maerhart in #5144
- [FIRRTL] Add LowerOpenAggs pass. by @dtzSiFive in #5137
- [FIRRTL] More defensive creation of Forceable declarations. by @dtzSiFive in #5148
- [FIRRTL] Fix incorrect getSingleConnectUserOf when > 1 connect. by @dtzSiFive in #5150
- [Arc] Add reset and enable grouping pass by @TaoBi22 in #5103
- [CI] Bump CI image by @mortbopet in #5155
- [CHIRRTL] Use InnerSymbolOpInterface on cmem and smem. by @dtzSiFive in #4874
- [FIRRTL][FIRParser] Parse mixed aggregates into open agg/sub ops. by @dtzSiFive in #5128
- [ExportVerilog] Allow
$
to be in the identifier by @uenoku in #5160 - [DC] Add rationale and boilerplate by @mortbopet in #5156
- [SV] Macro definitions and declarations with arguments by @darthscsi in #5149
- Bump LLVM by @maerhart in #5165
- [Arc] Dedup: generalize to CallOpInterface by @maerhart in #5161
- [FIRRTL] Canonicalize refresolve(forceable.ref) -> forceable.data. by @dtzSiFive in #5170
- [DC] Add ops and types by @mortbopet in #5157
- Bump LLVM by @fabianschuiki in #5172
New Contributors
- @frog-in-the-well made their first contribution in #3991
- @mmaloney-sf made their first contribution in #4911
Full Changelog: firtool-1.40.0...firtool-1.41.0
Firtool Release 1.40.0
What's Changed
- [ESI][Data windows] Introduce wrap/unwrap by @teqdruid in #4953
- [HW] Size enums to the number of tags by @darthscsi in #4988
- [FIRRTL] Add MemOp prefix attr, remove groupID attr by @fabianschuiki in #4952
- [Arc] Memory ops: optional enables and folders by @maerhart in #4976
- [Arc] Add StateOp folder by @maerhart in #4979
- [FIRRTL] lower plusargs to initial block by @darthscsi in #4999
- [FIRRTL] Parse {force,release}{,_initial}. by @dtzSiFive in #4990
- [Seq] Add enums for RUW/WUW behavior of memories by @fabianschuiki in #5007
- [FIRRTL] Add
getFieldNameAttr
helper to SubTagOp by @youngar in #5016 - [HW] Add type inference to UnionExtractOp by @youngar in #5015
- [FIRRTL] Lower complex enums to use hw enums for the tag by @youngar in #5019
- [ExportVerilog] Handle printing of union types by @youngar in #5020
- [ExportVerilog] Union type output support by @teqdruid in #5001
- [InferWidths] Add support for inferring through ref.sub. by @dtzSiFive in #5000
- [FIRRTL][InferResets] Infer through ref.sub. by @dtzSiFive in #4998
- [PyCDE] [Docs] Mention to add upstream remote to fetch tags when building wheels by @VMois in #5027
- [Handshake] Remove cmerge return type inference by @RamirezLucas in #5021
- [Arc] StripSV: fix dialect dependencies, option and warning for replacing external module instances by @maerhart in #5028
- [ExportVerilog] Handle printing of
UnionExtractOp
by @youngar in #5022 - [HW] implement missing EnumConstantOp builder by @youngar in #5030
- [HW] Add an enum comparison operation by @youngar in #5032
- Bump LLVM by @youngar in #5029
- [FIRRTL][Dedup] Print integer constants as hexadecimal by @youngar in #5033
- [Docs] Include Arc and SystemC in Passes.md by @maerhart in #5036
- [ExportVerilog] Add support for
EnumCmpOp
by @youngar in #5035 - [FIRRTL] Add
MatchOp
statement by @youngar in #5037 - [FIRRTL] Add
IsTagOp
to test enumeration variant by @youngar in #5038 - [FIRRTL] Add LowerMatches pass by @youngar in #5039
- [Seq] Add an option to lower
seq.compreg
toalways
blocks by @nandor in #5040 - [FIRRTL][LowerToHW] Handle SubTag and IsTag operations by @youngar in #5041
- [FIRRTL] Support EnumTypes in
walkGroundTypes(Type)
utility by @youngar in #5042 - [Arc] Infer StateOp reset from CompReg by @TaoBi22 in #4997
- [Arc] Remove erroneous reset nesting in LowerState pass by @TaoBi22 in #5023
- [FIRRTLFolds] Fix crashes in bundle/vector create folders. by @dtzSiFive in #5048
- [FIRRTL] Alternative Connect/Invalidate Parsing by @seldridge in #5049
- [LowerTypes][NFC] Minor touchups. by @dtzSiFive in #5050
- Enable
--view-op-graph
for circt-opt by @mortbopet in #5046 - [ESI][Windows] Lower Window ports to unions by @teqdruid in #5026
- [Handshake] Remove handshake.select by @mortbopet in #5045
- Bump LLVM by @chick in #5054
- [LoopSchedule] Move PipelineWhile and related ops from Pipeline to LoopSchedule by @andrewb1999 in #4947
- [NFC][Support] Factor out TypeConversionPattern into support lib by @teqdruid in #5055
- [NFC][ESI] Refactor ESI passes into individual files by @teqdruid in #5058
- [ESI][MSFT] Fix all clang-tidy-10 warnings by @teqdruid in #5059
- [FIRRTL] Parse 3.0.0 connect and invalidate by @seldridge in #5057
- [PyCDE] Expose ESI list type by @teqdruid in #5060
- [ESI] Fix capnp relative include paths after refactor. by @dtzSiFive in #5061
- [FIRRTL] Uninferred Width Cast by @darthscsi in #5047
- [ETC] Don't relocate instances that were only in extracted test code. by @mikeurbach in #5064
- [Arc][LowerState] Fix combinational loop false positives by @fabianschuiki in #5068
- [FIRRTL] Add clock gate intrinsic by @fabianschuiki in #5073
- LLVM Bump by @nandor in #5070
- [FIRRTL] FoldReadWritePorts: Fix heap-use-after-free. by @dtzSiFive in #5078
- [FIRRTL][InferWidths] Support enum types by @youngar in #5079
- [ExportVerilog] Add support for UnionCreate op. by @youngar in #5081
- [FIRRTL] firtool: Run merge-cnxns regardless of agg preserv. by @dtzSiFive in #5086
- [OM] Add a Reference type. by @mikeurbach in #5083
- [OM] Add Reference attribute. by @mikeurbach in #5084
- [FIRRTL] RefType: Implement FieldIDTypeInterface. by @dtzSiFive in #5087
- [Seq] Add clock gate operation by @fabianschuiki in #5082
- [FIRRTL][LowerToHW] Support FEnumCreateOp by @youngar in #5080
- [ExportVerilog] Remove uneeded parenthesis around UnionCreate by @youngar in #5091
- [FIRRTL][ExpandWhens] Use port locs when emitting init errors by @youngar in #5092
- [FIRRTL] Remove some unused datastructures by @youngar in #5093
- [FIRRTL] Support multiple ports for smem by @SpriteOvO in #4850
- [LowerToHW] Gate force/release on ifndef SYNTHESIS, not VERILATOR. by @dtzSiFive in #5090
New Contributors
Full Changelog: firtool-1.39.0...firtool-1.40.0