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  1. genome / pindel

    Pindel can detect breakpoints of large deletions, medium sized insertions, inversions, tandem duplications and other structural variants at single-based resolution from next-gen sequence data. It uses a pattern growth approach to identify the breakpoints of these variants from paired-end short reads.

    SystemVerilog • Built by @liangkaiye @EWLameijer @jmarshall @nnutter @acoffman

  2. rdsalemi / uvmprimer

    Contains the code examples from The UVM Primer Book sorted by chapters.

    SystemVerilog • Built by @rdsalemi

  3. VerificationExcellence / SystemVerilogReference

    training labs and examples

    SystemVerilog • Built by @mramdas

  4. swetland / zynq-sandbox

    a playground for xilinx zynq fpga experiments

    SystemVerilog • Built by @swetland @travisg

  5. unihd-cag / openhmc

    openHMC - an open source Hybrid Memory Cube Controller

    SystemVerilog • Built by @jurischmidt

  6. UCLONG / NetEmulation

    Software Simulation and Hardware Synthesis of Electrical and Optical Interconnection Networks

    SystemVerilog • Built by @DannyNicholls @BorisDosen @pmwatts @ridwanmadarbux @p-andreades

  7. cjdrake / AES

    Advanced Encryption Standard (AES) SystemVerilog Core

    SystemVerilog • Built by @cjdrake

  8. VerificationExcellence / SystemVerilogAssertions

    Examples and reference for System Verilog Assertions

    SystemVerilog • Built by @mramdas

  9. iDFLO / ece337project

    Spring 2014 ECE 337 project

    SystemVerilog • Built by @iDFLO

  10. jeras / rp8

    RISC processor 8bit (AVR ISA), RTL based on 'navre'

    SystemVerilog • Built by @jeras

  11. VerificationExcellence / UVMReference

    Reference examples and short projects using UVM Methodology

    SystemVerilog • Built by @mramdas

  12. amiq-consulting / amiq_apb

    SystemVerilog VIP for AMBA APB protocol

    SystemVerilog • Built by @amiq-consulting

  13. rdustinb / fpga_functions

    Repository captures many of the FPGA Logic cores I have created

    SystemVerilog • Built by @rdustinb

  14. dovstamler / uvm_agents

    UVM agents

    SystemVerilog • Built by @dovstamler

  15. yctsai88 / uvmprimer

    Contains the code examples from The UVM Primer Book sorted by chapters.

    SystemVerilog • Built by @rdsalemi

  16. luuvish / system-verilog-patterns

    SystemVerilog Design Patterns

    SystemVerilog • Built by @luuvish

  17. kouamano / SOC

    k-means

    SystemVerilog • Built by @kouamano

  18. sidharthms / asic-edge-detector

    Canny Edge Detector in Verilog

    SystemVerilog • Built by @ssabpisa @sidharthms @hxiong @beaslrya

  19. freecores / aes_decrypt_fpga

    AES Decryption Core for FPGA

    SystemVerilog •

  20. tenthousandfailures / uniquecoverage

    unique coverage classes

    SystemVerilog • Built by @tenthousandfailures

  21. jeras / riscv_asm_sv

    RISC-V assembler/dis-assembler written in SystemVerilog

    SystemVerilog • Built by @jeras

  22. bosson / balancebook

    Web ledger based on EU and SE bookkeeping standards, xml, xslt, servlets and jquery

    SystemVerilog • Built by @bosson

  23. ljepson74 / svsc

    SystemVerilog and UVM examples

    SystemVerilog • Built by @ljepson74

  24. aaronferrucci / dcpu16-model-SystemVerilog

    Behavior model of the DCPU-16, in SystemVerilog.

    SystemVerilog • Built by @aaronferrucci

  25. doswellf / combinator-uvm

    UVM Testbench For SystemVerilog Combinator Implementation

    SystemVerilog • Built by @doswellf

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