adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
OpenTitan: Open source silicon root of trust
A simple parametrizable doorbell based mailbox
AXI X-Bar
An energy-efficient RISC-V floating-point compute cluster.
RISC-V Debug Support for our PULP RISC-V Cores
SystemVerilog modules and classes commonly used for verification
Generic Register Interface (contains various adapters)
AXI Adapter(s) for RISC-V Atomic Operations
Common SystemVerilog components
Pipelines the AXI path with FIFOs
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RSD: RISC-V Out-of-Order Superscalar Processor